In FIG. 1, bitlines for accessing an array of memory locations are grouped into bytes in a prior art data selection schematic 100. Eight bitlines (e.g., BL07, BL06, . . . , BL00) are grouped into a byte. For BYTE 0 the eight bits are organized from most significant to least significant positions as BL07, BL06, . . . , BL00. A plurality of bytes of bitlines (BYTE 0, BYTE 1, . . . , BYTE n) represent n+1 bytes of bitlines used for accessing the array of memory locations. In BYTE 0 the eight bitlines connect to a respective set of column latches (CL07, CL06, . . . , CL00) used to store write data. Connections to a plurality of bit memory locations (not shown) lay along the extent of a bitline. A memory location is selected for access in a reading or writing operation when its respective bitline and a wordline (not shown) are selected. The wordline typically addresses one or more bytes of bit memory locations. The bitline is a primary electrical communication element feeding into an access network providing connection of the memory locations to a read or write circuit.
Bitlines for a byte of memory locations are selected by a group of eight bitline select transistors. For instance, for BYTE 0, eight bitline select transistors BLST07, BLST06, . . . , BLST00 are selected in parallel. Other sets of eight bitline select transistors (BLST17, BLST16, . . . , BLST10; . . . ; BLSTn7, BLSTn6, . . . , BLSTn0) operate similarly. A bitline select transistor is typically an NMOS field effect transistor. At any time, one of the n+1 byte select lines (BS0, BS1, . . . , BSn) is activated enabling connection of one byte of bitlines to a set of eight global bitlines (GBL7, GBL6, . . . , GBL0). A byte select controller 150 ensures that only one byte select line is activated at a time. Only a single byte is selected at one time. The byte select controller 150 ensures a single byte is selected by only enabling one of the byte select lines (BS0, BS1, . . . , BSn) at a time.
The global bitlines provide connection for a single bit position across all bytes of the array of memory locations. The global bitline (GBL7) for bit position seven, for instance, connects to a bitline in the seventh bit position (BL07, BL17, . . . , BLn7) of any byte selected in the memory array. Eight bit select transistors (BST7, BST6, . . . , BST0) provide connection of the global bitlines to a source line 188. A global bitline connection is achieved when one of eight respective bit select lines (BSL7, BSL6, . . . , BSL0) at a time receives a select signal from a bit select controller 185. The source line 188 connects to an input of a sense amplifier 195 and an output of a write data loading logic block 190. The sense amplifier 195 and the write data loading logic block 190 are the circuits used in a read operation and a write operation respectively.
With reference to FIG. 2, byte select signals coincide with bit select signals in a prior art data selection waveform 200 to control a bitline selection. Each of the n+1 byte select signals (BYTS0, BYTS1, . . . , BYTSn) corresponds to a respective byte select line (BS7, BS6, . . . , BS0) of FIG. 1. In a sequential access operation, one of n+1 byte select signals is activated for eight cycles at a time. Each of the eight cycles of one of the n+1 byte select signals (BYTS0, BYTS1, . . . , BYTSn) correspond to a sequence through eight bit selects signals (BSS7, BSS6, . . . , BSS0). The eight bit select signals (BSS7, BSS6, . . . , BSS0) are applied to the respective eight bit select lines (BSL7, BSL6, . . . , BSL0) of FIG. 1. A memory location in BYTE 0 bit position seven (BL07) is accessed when a corresponding wordline, a first cycle of byte select signal zero (BYTS0), and bit select signal seven (BSS7) are active. In a write operation, bit select signal seven (BSS7) activates bit select transistor seven (BST7) and byte select signal zero (BYTS0) activates bitline select transistor zero-seven (BLST07) establishing an electrical connection between the write data loading logic block 190 and a column latch zero-seven (CL07) of BYTE 0.
In the case of a large memory and correspondingly large global bitlines, any one of the global bitlines may become charged to a high voltage level during a write cycle. During extremely low frequency operation and due to capacitive losses, a high voltage level on a global bitline may be discharged over time to a voltage level low enough to be recognized as a low logic level. No active source maintains the high voltage level on the global bitline until a successive write cycle at the same bit position. The global bit line is coupled to a corresponding column latch during each of the eight write cycles of the associated byte. On a succeeding access, due to discharging of the global bitline, a low logic level will be coupled to a column latch. The global bit line has sufficiently large capacitance, that when charge sharing occurs during coupling to the relatively small capacitance of the column latch, the low logic level on the global bit line effectively writes a low logic state to the column latch.